FPGA-based coprocessor for real-time SENSE reconstruction: Design and Implementation

In real-time clinical settings, high speed systems have become imperative to meet the large data processing requirements of parallel MRI algorithms e.g. SENSE. Field-Programmable-Gate-Arrays (FPGAs) have recently emerged as a viable solution to adhere the rising demands of fast data processing by exploiting the inherent parallelism of SENSE reconstruction algorithm. This paper presents the first design effort to implement high performance 32-bit floating-point FPGA-based coprocessor for real-time SENSE reconstruction using high-level-synthesis (HLS) frame work. In-vivo results of 8-channel 1.5T human-head dataset show that the proposed system speeds up the image reconstruction time up to 1000x without compromising the image quality.